Resumen

AGOSTINI, L. et al. Forward and inverse 2-D DCT architectures targeting HDTV for H.264/AVC video compression standard. Lat. Am. appl. res. [online]. 2007, vol.37, n.1, pp.11-16. ISSN 0327-0793.

This paper presents the architecture and the VHDL design of the integer Two-Dimensional Discrete Cosine Transform (2-D DCT) used in the H.264/AVC codecs. The forward and inverse 2-D DCT architectures were designed and their synthesis results mapped to Altera FPGAs are presented. The 2-D DCT calculation is performed by exploring the separability property, in such way, each 2-D DCT architecture is divided in two 1-D DCT calculations that are joined through a transpose buffer. The 1-D DCT transforms implemented and herein described are multiplierless, hence optimized shift-add operations are used. The architectures have a dedicated pipeline, optimized to process one input data per clock cycle. These architectures are able to cope with H.264/AVC encoder or decoder requirements targeting High Definition Digital Television (HDTV), with 1920x1080 pixel/frame at 30 frames per second.

Palabras clave : H.264/AVC Video Compression; Dedicated Hardware for Video Compression; 2-D FDCT; 2-D IDCT; Integer Transforms.

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