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Latin American applied research

versión impresa ISSN 0327-0793


LIBERATORI, M. C.  y  BONADERO, J. C.. AES-128 cipher: Minimum area, low cost FPGA implementation. Lat. Am. appl. res. [online]. 2007, vol.37, n.1, pp. 71-77. ISSN 0327-0793.

The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen and recently selected as the official Advanced Encryption Standard (AES) is well suited for hardware use. This implementation can be carried out through several trade-offs be-tween area and speed. This paper presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher. Selected FPGA Family is Altera Flex 10K. The cipher operates at 25 MHz and consumes 286 clock cycles for algorithm encryption or decryption, resulting in a throughput of 11 Mbps. Synthesis results in the use of 957 logic cells and 6528 memory bits. The design target was optimization of area and cost.

Palabras clave : FPGA; Cryptography; AES; Cipher; VHDL.

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