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Latin American applied research

versión impresa ISSN 0327-0793

Lat. Am. appl. res. v.35 n.2 Bahía Blanca abr./jun. 2005


Development of a state feedback controller for the synchronouns buck converter

A. Oliva1, H. Chiacchiarini2 and G. Bortolotto

Instituto de Inv. en Ing. Eléctrica "Alfredo Desages"
Dto. Ing. Eléctrica y Computadoras,
Universidad Nacional del Sur, Av. Alem 1253 (8000) Bahia Blanca, ARGENTINA


Abstract ¾ A digital control algorithm for a current-mode (CM) and a voltage-mode (VM) synchronous buck converter (SBC) is developed. In both cases, the design leads to a stable controller, even for a duty cycle larger than 50%. The desired output voltage and the transient response can be independently specified. Moreover, zero steady-state error in the output voltage can be obtained with the aid of additional dynamics. In both cases, the specification is done by pole placement using complete state feedback. A discrete-time model is used to design the feedback gains. Both the stability and the small-signal transient response are analyzed. In another paper (Oliva et al., 2003) the control algorithms are experimentally validated with a DSP-controlled SBC.

Keywords ¾ Switch-Mode Power Supplies. Digital Control. Buck Converter.


Switch-mode power supplies (SMPS), like the buck converter, are frequently used in the current or the voltage modes of operation. Current-mode control is commonly used due to its intrinsic current limiting, providing a natural over-current protection. This characteristic allows to parallel modules to extend the current capability (Brown and Midlebrook, 1981).

Since CM SMPS show an instability (evident as a subharmonic oscillation) when the duty cycle is larger than 50%, the industry has adopted the external ramp compensation method to cancel out the oscillations. This method consists on adding an artificial ramp to the reference or to the current waveform (Unitrode, 1995; Brown and Midlebrook, 1981). It is a simple method, but it does not allow to arbitrarily place the closed-loop poles to achieve a desired dynamic response.

SMPS have traditionally been modeled with the averaged-state model, introduced by Cûk (Midlebrook and Cuk, 1976). However, this model does not explain the CM instability.

The origin of the CM instability is conveniently explained by another modeling technique, introduced by Packard (1976), known as discrete modeling, and by the sampled-data model from Brown (Brown and Midlebrook, 1981). These techniques are used in this work to obtain the discrete model of the switching converter, followed by a complete state feedback to adjust the closed-loop dynamics. The small-signal stability and transient response for this model are latter analyzed. The instability is completely eliminated from the CM converter, yielding a determined dynamic response. The regulator was analyzed using a discrete modeling technique, as in Fang and Abed (2001). For the VM converter, the desired output voltage and the type of transient response that the regulator would exhibit due to perturbations or a set-point variation can be separately specified (this is a main difference between this method and the traditional sawtooth-and-threshold method). Moreover, with the aid of additional dynamics, zero steady-state error can be achieved on the output voltage. Summarizing, an alternative control strategy is introduced for SMPS operating in VM and CM. The algorithms were experimentally tested on a SBC-based voltage regulator. The experimental results are shown in Oliva et al. (2003).

A DSP was used to implement the controller. This is not an issue when the target is a high-current converter, because the DSP is a small portion of the overall cost. The use of a DSP has additional advantages, such as monitoring of critical variables, communication with other devices and possible on-line tuning of the dynamic response.


A. Continuous-time model

Switching converters are, in general, non-linear and time-variant circuits. Nevertheless, different models have been developed to describe the small-signal behavior of the system with linear equations (Brown and Midlebrook, 1981). The boost and the Cûk converters exhibit a non-linear function between the control variable and the output voltage. On the other hand, the buck converter is easier to control because that function is linear.

A discrete-time model for the switching converter capable of giving enough detail can be derived from the above mentioned techniques of Packard and Brown. In general, it is assumed that the periodic switching produces a change in the structure of the switching converter. Since the switch changes state twice per cycle, the system has two structures, one valid when the switch is on (ton) and another one valid when the switch is off (toff).

The SBC operates in the continuous-conduction mode with a constant switching frequency fs = 1/Ts. The following analysis shows the derivation of the model. Let: ic(t) the instantaneous current flowing through the capacitor; iL(t) the instantaneous current flowing through the inductor; Io the load current, assumed constant; and vd(t) the instantaneous input voltage. The current flowing through the inductor and the voltage across the capacitor are chosen as state variables.

Since the system has two different topologies during ton and toff, the SBC is characterized by two state equations. These two equations can be grouped into a single equation. To simplify the notation, the temporal dependency of the variable will be omitted, unless that would lead to a confusion. Thus, (t) will be written as .

The model for the SBC under constant load resistance, Rload, is the following: During ton of the nth switching period (n.Ts < t < (n + dn) Ts, where dn is the duty cycle):

Yielding u = v. Similarly, during toff, (n + dn)Ts < t < (n + 1) Ts:

Combining the equations during ton and toff into a single equation, yields (Brown and Midlebrook, 1981):


Notice that if dn is constant, the equation is linear with periodic coefficients. On the other hand, if the control is applied on dn the equation becomes nonlinear, because the duty cycle is a function of the state variables.

It is possible to derive a linear equation if the SBC operates under the small signal regime. The signals can be represented by a nominal value (in capital letters) plus a perturbation (in lowercase with 'ˆ'). Thus, the input voltage and the duty cycle will be written as vd = Vd + d, and dn = D + n, respectively. Therefore, d = d(t) can be written as a steady-state part (although it is time variant) , plus a perturbation, (Brown and Midlebrook, 1981): d = + , d' = 1 - d, are defined as:

Notice that these equations formally represent the effect of a perturbation of the duty cycle in the state equation. Likewise, the state vector can be represented by a steady-state component plus a perturbation:

Replacing in the state equation (1):

The state equation can be split in a nominal part plus a perturbation, as follows:

Making the perturbation equal to zero yields the steady-state equation:

and subtracting the last equation from the complete response, the equation for a perturbation in the state vector becomes:

This expression can be linearized neglecting the second-order terms, yielding:

Finally, (t) can be approximated by a train of impulses with the appropriate area, as it is done in (Brown and Midlebrook, 1981):

B. Discrete-time model

In this section it is found the discrete-time model of the SBC by integration of the small-signal state-space model over a switching period, Ts. Without lose of generality, it is choosen the initial integration time at (n + D)Ts. In the interval [(n + D)Ts, (n + 1)Ts] the switching functions are = 0, ' = 1, yielding:

Since the d function is non-zero only at (n + D)Ts, the integral yields:

Another approximation is done to evaluate this equation, assuming that the input voltage is constant during the integration interval. Therefore, the integral of the last term is zero. This approximation implies that the input voltage is not considered as a perturbation input; nevertheless, this does not affect the stability analysis. By analogy, during the interval [(n + 1)Ts, (n + D + 1)Ts] the state equation reduces to:

This equation is integrated using as the initial condition the value of the state vector found at the end of the previous period, [(n + 1)Ts], yielding:


which concludes the developing of the discrete-time model. This discrete model evaluates the behavior of the system due to small-signal perturbations (of duration n Ts) in the duty cycle.


A. Voltage Mode

A VM SBC requires a controller that compares an artificial saw-tooth waveform (STW) with a reference value, vref, to obtain the duty cycle corresponding to each individual cycle. Therefore, the VM SBC operates in a typical pulse-width modulation scheme (PWM).

The sensitivity of the duty cycle with respect to vref may be obtained by a geometric analysis. Consider the external STW with period Ts and amplitude Vp. For the nominal reference voltage, Vref, the nominal duty cycle, D, is given by . When a perturbation ref is applied on the reference voltage, it produces a variation on the duty cycle, , such as

. (3)

B. Current Mode

The CM SBC is controlled by changing the duty cycle based on variations of the peak value of the current flowing through the inductor. Therefore, it is necessary to find an expression for n as a function of the state and the control variables. The latter, Îp, is the perturbation on the peak value of the inductor current. For the small-signal model, an approximation for n using only the linear terms of its Taylor series expansion is proposed, yielding

. (4)

Evaluation of : To evaluate the sensitivity of the duty cycle with respect to the current flowing through the inductor it is convenient to analyze Fig. 1, that shows the variation of the duty cycle due to a perturbation îL > 0 in the current flowing through the inductor.

If the input and output voltages are considered constant during ton, then the slope of the ramp corresponding to the current flowing through the inductor does not change, and appears only a vertical shift given by îL. Thus,

, (5)

where is the slope of the ramp.

Evaluation of : To evaluate the sensitivity of the duty cycle with respect to the voltage across the capacitor refer to Fig. 2, that shows the dependency of the derivative of the current flowing through the inductor upon variations in the output voltage, vc. The equations corresponding to the nominal (r1) and perturbed (r') slopes are analyzed to obtain the expression of dn as a function of c :

Figure 1: Variation of the duty cycle due to a perturbation in the curent flowing through the inductor.

Figure 2: Variation of the duty cycle due to a perturbation on the output voltage.

Solving for n yields , and if c < < (Vd - Vc),

. (6)

Evaluation of : The sensitivity of the duty cycle with respect to the peak reference current, IP, can be found from Fig. 3. The peak current through the inductance, IP, will be changed by the control algorithm, and a perturbation in its value will change the nominal duty cycle. From Fig. 3 the reader can see that , where . Therefore,

. (7)


A. Voltage Mode

So far, it was developed a linear model for the SBC. An expression for the control scheme using complete state

Figure 3: Variation of the duty cycle due to a perturbation in the peak current through the inductor.

Figure 4: Digital tracking system with complete state feedback.

feedback is found in this section. From Eq. (3), the perturbation n in the duty cycle can be expressed as a function of the control variable. The discrete-time model for the SBC is given by Eq. (2). Replacing Eq. (3) in Eq. (2) yields

If complete state feedback is applied and the system is controllable, the closed-loop poles can be arbitrarily placed to yield a desired transient response. The negative feedback proportional to the states over ref is . The elements of the vector Fv determine the closed-loop poles of the system. Replacing vref in the system model gives

Using this control strategy a desired transient response can be achieved.

A.1. Extended state model of the regulator

The voltage regulator designed in the previous section was calculated under constant loading. This section develops a mechanism that allows the controller to track load changes and change the reference in order to keep the output voltage constant. This goal is achieved by the inclusion of additional dynamics, as shown in Fig. 4, that represents a digital tracking system with complete state feedback. The added dynamics are represented by Fa, Ga, L2 (Vaccaro, 1995).

A state space representation for the model represented in Fig. 4 is obtained defining a composite state vector:

where xa is the state vector of the additional dynamics. Then, to obtain the state space representation of the whole system, the cascade connection is explicitly used to construct its transition matrix and input matrix as

where c is the output matrix (relating the output y with the states x as y = c x). A regulator can be designed for the pair (Fd, Gd) yielding a feedback gain L := [ L1 L2 ], where L1 contains the first n elements of L, being n the order of the system to be controlled (for the SBC: n = 2). Vector L2 is the remaining part of L and relates the output ya with the states xa as ya = L2 xa. The gain L is calculated by pole placement. The whole procedure for obtaining (Fa, Ga) is detailed in Vaccaro (1995); however, in this case Fa = 1, Ga = 1. The main (and fundamental) advantage of this configuration is the fact that if the closed loop system is stable then the system will follow a constant reference with zero steady state error.

B. In Current Mode

In the sequel the control strategy to make the system to operate in current mode (CM) is shown. A complete state feedback is used. From Eq. (4), it is seen that n can be split in two parts: one due to the CM effects and the other due to the feedback. Then considering Eqs. (5), (6) and (7) it results

The discrete model for [(n + 1 + D)Ts] was found in (2), that is further simplified for the SBC case considering that A1 = A2 = A, and D' = 1 - D. Then

, (8)

where . Replacing n results

Grouping together the terms corresponding to the CM:

A state feedback is done on Îp to place the closed loop poles: and the closed-loop system becomes

, (9)

where FCL is the closed-loop system matrix.

Assuming controllability, the closed-loop poles can be arbitrarily placed by selecting the feedback gain F. Up to this point, nothing prevents the system to be stable for constant load and duty cycle over 50%.

B.1. Control with variable load

When the load is not constant, it is convenient to implement an observer for the load changes. An estimator for the load current is proposed as follows:

Io = iM - iC,

where iM is the average current in the inductor, obtained over a complete switching cycle, and iC is the average current in the output capacitor, which is different from zero over a load transient. Then:

. (10)

The current of the capacitor is estimated from approximating the derivative using finite differences as , where is the voltage of the capacitor sampled in the previous cycle. Then two new state variables are added to the discrete system: iM and . As a first step, iM is added as the third state variable in the continuous system and the new A matrix becomes

being the new state x = [ iL vc iM]T. The new matrix of the discrete system is

where j33 = 1 since the third state corresponds to a pure integrator. As it is necessary to implement Eq. (10), which corresponds to a resetable integrator (forcing iM to zero each time (n + D).Ts) it is observed that j13 = j23 = 0 so the state iM[(n + D).Ts] does not affect the value of the other states at the next sampling time. Also the product j33. iM[(n + D).Ts] º 0 due to the periodic reset of iM[(n + D).Ts]. The same effect (j33.iM = 0) is obtained forcing j33 º 0 instead of periodically reseting iM[(n + D).Ts].

Finally, the variable is added to the discrete system as the fourth state. Then the discrete system matrix Fe of the whole system results:

and the next state vector is x = [ iL vc iM ]T . Then the new discrete model is formally identical (replacing F and x with the new expressions) to Eq. (9) with respect to the effects of the perturbations on the duty cycle.

As a design alternative, the design procedure shown above for the VM can be used here for variable load adding additional dynamics, but it is not shown due to space limitation.


A digital controller was developed for a SBC in VM and CM using complete state feedback. The control scheme is based on the addition of a small corrective signal over the nominal control signal of the converter, so changing slightly the duty cycle to cancel perturbations keeping the output voltage constant.

The main difference with the traditional control strategy for the VM (proportional control with reference ramp) is that here it is possible to specify independently the output voltage level and the transient response of the system. Also, due to the additional dynamics, a zero steady-state error is guaranteed for the output voltage. The controller is designed by pole placement in the state space. The closed loop dynamics of the SBC in CM can be completely specified even for duty cycles over 50%.

The controllers obtained in this paper were experimentally tested on a SBC under different load conditions. The results are promising (Oliva et al., 2003) with stable behavior even under load variations.

This work was partially supported by PICT'98 3963 of ANPCYT and PGI UNS 24/K021.

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2. Fang, Ch. and E. Abed, "Sampled-data modelling and analysis of the power stage of pwm dc-dc converters", Int. J. of Electronics, 88, 347-369 (2001).         [ Links ]
3. Middlebrook, R. D. and S. Cûk, "A general unified approach to modelling switching converter power stages", IEEE Power Electronics Specialists Conference Record, 284-301 (1976).         [ Links ]
4. Oliva A., H. Chiacchiarini and G. Bortolotto, "Control por realimentación de estados del convertidor buck sincrónico: resultados experimentales", X RPIC, UTN FRSN San Nicolás, Argentina, I, 128-133 (2003).         [ Links ]
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6. Unitrode application note, U-97 (1995).         [ Links ]
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